Field programmable gate arrays (FPGAs) are devices which can be arbitrarily programmed to implement a wide variety of logic circuit designs. An FPGA typically contains an array of logic blocks, each of which can be configured to perform selected logic functions in response to the programming of the FPGA. Individual logic blocks are configured to represent the individual elements of the logic circuit design being implemented. I/O pins on the FPGA carry data, control and clock signals to and from the configured logic blocks as required by the implemented circuit design.
The size of a circuit design which can be implemented in an FPGA depends on the number of logic blocks in the FPGA and the number of I/O pins available to the FPGA for use in implementing the circuit design. I/O pin count is a function of the perimeter dimension of the FPGA and the distance between I/O pads required by existing wirebonding equipment. Hence, the number of I/O pins on a given FPGA is proportional to die size, and only increases relatively slowly with advances in assembly equipment. The number of logic blocks which can be placed on an FPGA, however, is proportional to the square of the die size and is growing rapidly as the size of functional devices which can be fabricated on silicon continues to shrink. Continued reduction in the physical dimensions of integrated circuit devices such as FPGAs is therefore imposing a severe bottleneck with respect to I/O pin availability. Under these circumstances, it would be desirable to provide a means for reducing or avoiding the I/O availability bottleneck which otherwise limits the size of circuit designs which can be implemented in an FPGA.